1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particular to a liquid crystal display device of an active matrix type, which uses a TFT (i.e., Thin Film Transistor) as a switching element of the device.
2. Description of the Related Art
In general, the liquid crystal display device is advantageous in that reduction of the device is possible in its thickness, weight and also in its power consumption. Consequently, in recent years, the liquid crystal display device is extensively used in information equipment, AV (i.e., Audio Visual) equipment and like equipment. Of these liquid crystal display devices, particularly, the liquid crystal display device of the active matrix type has a construction in which a plurality of pixels are driven by their corresponding switching elements. Further, of these active matrix type liquid crystal display devices, particularly, one using the TFT as its switching element is in principle not dependent upon the number of scanning cycles in sharpening an image being displayed. In addition to such sharp contrast, the active matrix type of liquid crystal display device having the TFT is advantageous in a high speed display mode. Consequently, the active matrix type of liquid crystal display device is advantageously used in large display screens and also in high definition motion display units.
Conventionally, the TFT has been produced so as to have a reversed stagger construction, in which a channel region is formed over a gate electrode by applying both a thin-film forming technology and a lithography technology in a transparent insulation substrate made of glass and like materials.
FIGS. 9 and 10 show in construction a plan view and a cross-sectional view of one of pixels of the conventional active matrix type of liquid crystal display device, respectively, wherein: the cross-sectional view is taken along the line C--C of FIG. 9; and, the active matrix type of liquid crystal display device is provided with the TFT having such reversed stagger construction, and is hereinafter referred to simply as the liquid crystal display device.
In a construction shown as in FIGS. 9 and 10: a gate electrode 32 is formed on a transparent insulation substrate 31; connected with this gate electrode 32 is a gate bus wiring 33; the gate electrode 32 is covered with a gate insulation film 35; a semiconductor layer 36 assuming a longitudinally elongated shape is formed in a portion of the gate insulation film 35; and, each of a drain electrode 39 and a source electrode 40 is formed in each of opposite ends of this semiconductor layer 36 through a contact layer 37. Formed in the source electrode 40 is a transparent pixel electrode 42. Extending from the drain electrode 39 is a drain bus wiring 38 which extends in a direction substantially perpendicular to a longitudinal direction of the gate bus wiring 33. Formed under the transparent pixel electrode 42 are an auxiliary capacitance wiring 44 and an auxiliary capacitance electrode 45.
A TFT 50 having the reversed stagger construction is constructed of: the gate electrode 32; a semiconductor layer 36; a contact layer 37; a drain electrode 39; and, the source electrode 40. In the TFT 50, a channel region formed on a surface of the semiconductor layer 36 disposed over the gate electrode 32 is placed under the control of the gate electrode 32. Further, all the semiconductor layer 36, drain electrode 39, source electrode 40 and the transparent pixel electrode 42 are covered with a protective film 43.
On the other hand, a transparent insulation substrate 51 corresponding to the transparent insulation substrate 31 is formed. A portion of this transparent insulation substrate 51 is formed into a colored layer 52. Further, a light shield layer 53 is formed in a position corresponding to that of the TFT 50. A transparent common electrode 54 is so formed as to cover both the light shield layer 53 and the colored layer 52.
In the above construction, a liquid crystal layer 55 is sealed in between: the transparent insulation substrate 31 on which the TFT 50 is formed; and, the transparent insulation substrate 51 formed over the transparent common electrode 54, so that the conventional liquid crystal display device is formed.
In the conventional liquid crystal display device having the above construction, the gate bus wiring 33 is connected with scan lines (not shown) through which scanning signals are applied to the gate bus wiring 33. On the other hand, connected with the drain bus wiring 38 are signal lines (not shown), to which video signals are applied to operate the liquid crystal display device.
Next, a method for driving the conventional liquid crystal display device will be described.
FIG. 7 shows a circuit equivalent in function to one of pixels of the above conventional liquid crystal display device, in which: the reference character C.sub.GS denotes a parasitic capacitance between the gate electrode 32 and the source electrode 40; the reference character C.sub.LC denotes a capacitance of the liquid crystal; and, the reference character C.sub.SC denotes a holding capacitance.
Further, FIG. 8 shows timing charts of various electric signals in the drive mode of the conventional liquid crystal display device.
In operation, in a condition in which a predetermined signal voltage V.sub.D is applied to the source electrode 40 from the signal lines, a fist row of the matrix is scanned at first, so that a gate voltage V.sub.GON serving as a selecting signal is applied to the gate electrode 32 through the gate bus wiring 33, whereby all the TFTs of the pixels connected with the first row of the matrix are turned ON, which causes a potential level V
of the transparent pixel electrode 42 of each of the TFTs 50 to be equal to the signal voltage V.sub.D. PA1 Where: .DELTA.V.sub.G =(V.sub.GON -V.sub.GOFF)
Next, when a second row is scanned, the gate voltage of the gate electrode 32 of each of the first row's pixels decreases to a voltage of V.sub.GOFF, which turns OFF the TFTs 50 of the first row's pixels. However, since each of the TFTs 50 functions as a memory element because of the presence of: the parasitic capacitance C.sub.GS between the gate and the source electrode; a liquid crystal capacitance C.sub.LC and the holding capacitance C.sub.SC, the above-mentioned potential level V.sub.P1 of the transparent pixel electrode 42 of each of the TFTs 50 remains at the same potential level as that V.sub.D of the signal line. Consequently, the liquid crystal 55 has its molecules vary in their orientation on the basis of such potential level V.sub.P1. As a result, due to rotary polarization of the liquid crystal, each of the pixels of the display unit is modified in its transmission light, which enables to display an image on the display unit as a whole.
On the other hand, the potential level V.sub.P1 of the transparent pixel electrode 42 is held at the same potential level as that of the signal potential level V.sub.D, but actually the potential level V.sub.P1 of the transparent pixel electrode 42 reduces from the potential level V.sub.D by the amount of a potential of .DELTA.V under the influence of the presence of: the parasitic capacitance C.sub.GS ; liquid crystal capacitance C.sub.GL and the holding capacitance C.sub.SC at a time when the TFT 50 is turned OFF, i.e., when the gate voltage is reduced from a voltage of V.sub.GON to a voltage of V.sub.GOFF. In the above, the potential of .DELTA.V is called the feed-through voltage which is given by the following equation (1): EQU .DELTA.V=.DELTA.V.sub.G (C.sub.GS /(C.sub.GS +C.sub.LC +C.sub.SC)) (1)
As is clear from the above equation (1), the feed-through voltage .DELTA.V is proportional to the parasitic capacitance C.sub.GS between the gate and the source electrode. Consequently, it is preferable to reduce the parasitic capacitance C.sub.GS.
Here, as shown in FIG. 8, with respect to the signal potential level V.sub.D which is applied from the signal line to the drain electrode 39 through the drain bus wiring 38, an AC current having its polarity reversed at every frame of a picture to be scanned is used in order to prevent the liquid crystal layer 55 from suffering from any burning problem. Consequently, the transparent pixel electrode 42 also has its potential V.sub.P1 reversed in polarity. In this case, however, as described above, since its potential level V.sub.P1 described above reduces from the potential level V.sub.D by the amount of a potential of .DELTA.V, it is necessary to set a potential level V.sub.COM of the transparent common electrode 54 of the side of the transparent insulation substrate 51 so as to be smaller than a central potential level of V.sub.c by the potential of .DELTA.V (i.e., V.sub.COM =V.sub.C -.DELTA.V).
As a result, as shown in FIG. 8 in hatched area, a potential or voltage applied to the liquid crystal layer 55 assumes a waveform which is symmetric with respect to a neutral line extending horizontally between a positive and a negative area of the timing chart shown in FIG. 8. When a potential or voltage applied to the liquid crystal layer 55 does not assume such a symmetric waveform, this results in a so-called flicker phenomenon or problem causing an image on a screen of the display unit to flicker. In this case, in addition to such flicker phenomenon or problem, there is another advantageous phenomenon, i.e., burning phenomenon of a screen in the display unit since the screen is continuously subjected to a DC current caused by an asymmetric component of the voltage or potential having been applied to the liquid crystal layer 55.
On the other hand, fabrication of the TFTs 50 onto the transparent insulation substrate 31 is realized by combination of: a thin film deposition technology represented by, for example such as sputtering processes, CVD (i.e., Chemical Vapor Deposition) processes and like processes; and, a photolithography technology. Namely, in the above fabrication, it is necessary to repeat mask alignment operations of a plurality of masks having various patterns so as to repeatedly perform patterning operations of both the insulation films and the conductive films of the device. In this case, however, due to the presence of limits in an accuracy of mechanical positioning operations, some misalignment inevitably occurs in the mask alignment operations.
Consequently, in fabrication of each of the TFTs 50, particularly, in fabrication of the gate electrode 32 and the source electrode 40, the above-mentioned misalignment causes a hatched area of FIG. 9 to vary in area size, provided that: through such hatched area of FIG. 9, the gate electrode 32 and the source electrode 40 are disposed in an overlapping relationship with each other. Due to this, the parasitic capacitance C.sub.GS between the gate and the source electrode varies. Consequently, as is clear from the above equation (1), the feed-through voltage or potential of .DELTA.V varies. This permits the flicker phenomenon, burning phenomenon and like disadvantageous phenomena or problems to take place. In order to prevent these disadvantageous phenomena or problems from taking place, it is necessary to individually control the potential level V.sub.COM of the transparent common electrode 54.
Here, in order to reduce the amount of misalignment in the mask alignment operation, there is one of conventional ideas that a mask is divided into a plurality of small mask areas, for example, into a pair of small mask areas A and B in use. However, in this case, there is a possibility that the small mask area A differs from the small mask area B in the amount of misalignment. In this case, with respect to an optimum value of the potential level V.sub.COM of the transparent common electrode 54, these small mask areas A and B differs from each other, which makes it impossible to have one of these small mask areas A and B be free from the flicker phenomenon and like disadvantageous phenomena. This is another problem inherent in the prior art.
The following Japanese Laid-Open Patent Application No. Hei06-110081 (hereinafter referred to as the first conventional sample) discloses a conventional liquid crystal display device which compensates for variations in parasitic capacitance C.sub.GS which appears between the gate and the source electrode of the TFT due to the presence of misalignment in mask alignment operations.
FIG. 11 shows a plan view of the conventional liquid crystal display device disclosed in the first conventional sample, in which: each of a gate electrode 32 and a compensating gate electrode 61 is so arranged as to extend in a direction perpendicular to a longitudinal direction of a gate bus wiring 33; and, a compensating source electrode 62 is disposed over both the source electrode 40 and the compensating gate electrode 61 in a partially overlapping relationship therewith. Incidentally, in FIGS. 9 and 10, the parts which are the same as ones in FIG. 11 have been given the same reference numerals, and, therefore are not further explained hereinafter.
In the construction as shown in FIG. 11, even when a gate pattern and a source pattern are vertically or horizontally misaligned in a mask alignment process, it is possible to keep the parasitic capacitance C.sub.GS appearing between the gate and the source electrode at a constant value, because the sum in area size of: a left-hand hatched area of the Figure through which the source electrode 40 is disposed in an overlapping relationship with the gate electrode 32; and, a right-hand hatched area of the Figure through which the compensating source electrode 62 is disposed in an overlapping relationship with the compensating gate electrode 61 does not vary.
FIG. 13 shows a plan view of a liquid crystal display device disclosed in Japanese Laid-Open Patent Application No. Hei04-68319 (hereinafter referred to as the second conventional sample), in which: a gate electrode 32 disposed substantially perpendicular to a gate bus wiring 33 is extended to form: a compensating gate electrode 65 in its front end portion; and, a compensating source electrode 66 which is formed so as to be turned towards the left side portion of the compensating gate electrode 65, and thereby partially overlapping with the compensating gate electrode 65.
In the construction as shown in FIG. 13 described above, even when a gate pattern and a source pattern are vertically or horizontally misaligned in a mask alignment process, it is possible to keep the parasitic capacitance C.sub.GS appearing between the gate and the source electrode at a constant value, because the sum in area size of: an upper hatched area of the Figure through which the source electrode 40 is disposed in an overlapping relationship with the gate electrode 32; and, a lower hatched area of the Figure through which the compensating source electrode 66 is disposed in an overlapping relationship with the compensating gate electrode 65 does not vary.
FIG. 14 shows a plan view of a liquid crystal display device disclosed in Japanese Laid-Open Patent Application No. Hei 04-3124 (hereinafter referred to as the third conventional sample), in which: a pair of gate electrodes 32 and 34 are disposed substantially perpendicular to a gate bus wiring 33; a drain electrode 39 is disposed between the gate electrodes 32 and 34 in a partially overlapping relationship with these gate electrodes 32 and 34; and, a pair of source electrodes 40 and 41 are disposed outside the gate electrodes 32 and 34 in a partially overlapping relationship with these gate electrodes 32 and 34, respectively.
Here, it is necessary to form a pair of semiconductor layers 36 and 46 corresponding to the pair of the gate electrodes 32 and 34, respectively. Consequently, in this third conventional sample, with respect to each of the pixels, a pair of TFTs are formed.
In the above construction as shown in FIG. 14, even when a gate pattern and a source pattern are vertically or horizontally misaligned in a mask alignment process, it is possible to keep the parasitic capacitance C.sub.GS appearing between the gate and the source electrode at a constant value, because the sum in area size of: a left-hand hatched area of the Figure through which the source electrode 40 is disposed in an overlapping relationship with the gate electrode 32; and, a right-hand hatched area of the Figure through which the source electrode 41 is disposed in an overlapping relationship with gate electrode 34 does not vary.
FIG. 15 shows a plan view of a conventional liquid crystal display device disclosed in Japanese Laid-Open Patent Application No. Sho62-95865 (hereinafter referred to as the fourth conventional sample), in which: a semiconductor layer 36 is formed so as to assume a longitudinally elongated shape; and, a gate electrode 32 is formed over the semiconductor layer 36 so as to be disposed substantially perpendicular to a drain bus wiring 38. The gate electrode 32 is constructed of: a first electrode 55 partially overlapping with an upper portion of a gate bus wiring 33; and, a second electrode 56 partially overlapping with a lower portion of the gate bus wiring 33.
Further provided in the fourth conventional sample are a pair of source electrodes 47 and 48, wherein: the source electrode 47 is oppositely disposed from the first electrode 55 so as to partially overlap with a lower portion of the gate bus wiring 33; and, the source electrode 48 is oppositely disposed from the second electrode 56 so as to partially overlap with an upper portion of the gate bus wiring 33. Consequently, a pair of TFTs are formed with respect to each of the pixels.
In the construction as shown in FIG. 15 described above, even when a gate pattern and a source pattern are vertically or horizontally misaligned in a mask alignment process, it is possible to keep the parasitic capacitance C.sub.GS appearing between the gate and the source electrode at a constant value, because the sum in area size of: a left-hand hatched area shown in the Figure through which the source electrode 47 is disposed in an overlapping relationship with the first electrode 55 of the gate electrode 32; and, a right-hand hatched area of the Figure through which the source electrode 48 is disposed in an overlapping relationship with the second electrode 56 of the gate electrode 32 does not vary.
FIG. 16 shows a plan view of a conventional liquid crystal display device disclosed in Japanese Laid-Open Patent Application No. Sho61-166587 (hereinafter referred to as the fifth conventional sample), in which: a gate electrode 32 formed substantially perpendicular to a gate bus wiring 33 has its portion bent so as to extend in a direction parallel to a longitudinal direction of the gate bus wiring 33; a semiconductor layer 36 is formed so as to cover both the gate bus wiring 33 and the gate electrode 32; and, a source electrode 40 is disposed so as to partially overlap with the portion of the gate electrode 32, which portion is parallel with the gate bus wiring 33.
In the construction shown in FIG. 16 described above, even when a gate pattern and a source pattern are vertically or horizontally misaligned in a mask alignment process, it is possible to keep the parasitic capacitance C.sub.GS appearing between the gate and the source electrode at a constant value, because the total area size of a hatched portion shown in FIG. 16, through which hatched portion the source electrode 40 is disposed in an overlapping relationship with the gate electrode 32 does not vary.
However, any of the liquid crystal display devices disclosed in the first to the fifth conventional samples fails to compensate for the variations in parasitic capacitance appearing between the gate and the source electrode, i.e., suffers from the following problems in compensating for such variations in parasitic capacitance, namely:
A first one of the problems inherent in the conventional devices is as follows: in the conventional device, it is necessary to additionally form a compensating pattern means serving as a gate electrode or a source electrode. Consequently, the conventional device increases in volume corresponding to such compensating pattern means, which increases a load of a drive circuit of the conventional device, and thereby impairing the device in responsivity.
A second one of the problems inherent in the conventional devices is as follows: when the compensating pattern means is additionally formed in the device, such formation of the compensating pattern means also impairs the device in its aperture ratio (i.e., a ratio of effective display area to pixel's unit area). For example, in the case of the first conventional sample shown in FIG. 11, this first conventional sample is inferior to another conventional liquid crystal display device of FIG. 12 in its aperture ratio, because both the compensating gate electrode 61 and the compensating source electrode 62 formed in the first conventional sample shown in FIG. 11 are not formed in another conventional liquid crystal display device of FIG. 12.
A third one of the problems inherent in the conventional devices is as follows: since the conventional device fails to sufficiently shield its peripheral portion from the light, its leakage current increases when the TFTs of the device are turned OFF, which brings forth poor contrast in display. In other words, as shown in FIG. 10, when the light is incident on the device in a direction of the arrow from the side of a transparent insulation substrate 31 which is not provided with any light shield layer in its side, this incident light is then reflected from a light shield layer 53 provided in the side of a transparent insulation substrate 51. After that, the thus reflected light reaches a semiconductor layer 36, which causes the leakage current to increase as is in each of the remaining conventional devices.
Further, in any device of the first to the third conventional samples, since the semiconductor layer is formed into a longitudinally elongated shape over an upper portion of the gate electrode which is branched off from the gate bus wiring so as to be substantially perpendicular to the gate bus wiring, the TFT is limited in construction to a longitudinally arranged type construction. Due to this, it is impossible for any one of the conventional devices to employ a TFT having a horizontally arranged type construction in which the semiconductor layer is formed into a horizontally elongated shape. This is another disadvantage inherent in the conventional device. In general, the TFT having a longitudinally arranged type construction is inferior in aperture ratio to the TFT having a horizontally arranged type construction due to the presence of its branched-off gate electrode.